1. Field of the Invention
The present invention relates to a data form converter, which converts data form from serial to parallel or from parallel to serial.
2. Description of the Related Art
LSI (Large Scale Integration) technology has been remarkably developed, so that an operating clock in an LSI has been increased to several hundred megahertz (MHz) and a signal transmission rate between LSIs has been increased to several gigabits per second (Gbps). However, a difference between an operating speed in an LSI and the signal transmission rate between LSIs is large. In order to allow an LSI to output/input data to/from outside, a parallel-to-serial (hereinafter, denoted by “parallel-serial”) converter may be provided at an output stage of the LSI so as to convert low-speed parallel data in the LSI into high-speed serial data, allowing the high-speed serial data to be output from the LSI to the outside. Moreover, by providing a serial-to-parallel (hereinafter, denoted by “serial-parallel”) converter at an input stage of the LSI, high-speed serial data can be input from the outside to the inside of the LSI.
In order to meet demands regarding data input and output between the LSI and the outside of the LSI, several serial-parallel converters for converting serial data into parallel data and several parallel-serial converters for converting parallel data into serial data have been proposed.
Japanese patent application Unexamined Publication No. 11-98101 discloses a serial-parallel converter having a plurality of 1:2 demultiplexer (DEMUX) modules connected in a multistage tree structure (see paragraphs [0016] and [00171], and FIGS. 4 and 5). In each stage, serial data is converted into parallel data at a specific conversion ratio such as 1:2, 1:4, 1:8, or 1:16. Thus, it is possible to perform serial-parallel conversion at a conversion ratio of 2 to the n-th power, wherein n is an integer greater than 0. Such a conventional serial-parallel converter, however, cannot convert serial data to parallel data at a ratio other than the ratio of 1:2n.
Japanese Patent application Unexamined Publication No. 2002-217742 discloses a serial-parallel converter having a first-stage 1:2 serial-parallel converter, two second-stage conversion sections, and a retiming circuit. The first-stage 1:2 serial-parallel converter divides an input serial data signal into an odd-number channel data signal and an even-number channel data signal, which are supplied to respective ones of the second-stage conversion sections. Each of the second-stage conversion sections includes two 1:2 serial-parallel converters and a flip-flop circuit, which are each supplied with different-phase clocks generated by a frequency divider (see paragraphs [0013]–[0015] and FIG. 1). The output data signals of the second-stage conversion sections enter theretiming circuit to produce a parallel data signal.
In addition, the frequency divider is connected to an on/off switch, by which the frequency divider is allowed to divide an input clock at a selected one of two frequency-division ratios. In other words, the serial-parallel converter can selectively-set two frequency-division ratios by turning the on/off switch on or off. Accordingly, this conventional serial-parallel converter has such an advantage that serial-parallel conversion can be performed at two different ratios only by designing a single converter. Please note that the number of conversion ratios corresponds to the number of states provided by the on/off switch.
In this conventional serial-parallel converter, however, plural frequency-divided clocks are generated by the frequency divider. Accordingly, it is necessary to pay attention to skews between these frequency-divided clocks. For example, at a position where data transfer occurs over different frequency-divided clocks, setup and hold time of the first and second flip-flop circuits may become severe. Thus, it is necessary to ensure that the setup time and hold time have a sufficient margin. This makes it more difficult to design the serial-parallel converter.
As for a parallel-serial converter, Japanese Patent Laid-Open Publication No. 8-65173 discloses a parallel-serial converter having an elastic memory and a frequency divider, allowing parallel-serial conversion without the need of using an outside timing signal. More specifically, the frequency divider generates a read clock by dividing a high-speed clock by a fixed number (4), that is, frequency-frequency-division ratio=1/4. Four-bit input parallel data is written into the elastic memory according to an outside timing clock and read from the elastic memory according to the read clock. A parallel-serial conversion timing pulse is generated by using the high-speed clock and the read clock. A parallel-serial converter uses the parallel-serial conversion timing pulse and the high-speed clock to convert the read 4-bit parallel data into high-speed serial data (see paragraphs [0016]–[0019] and FIG. 1).
In this conventional parallel-serial converter, the frequency divider divides the high-speed clock at the predetermined frequency-frequency-division ratio. Thus, this parallel-serial converter also has a problem that the number of bits of low-speed parallel data to be converted into serial data is uniquely determined by the frequency-frequency-division ratio of the frequency divider. As a result, in order to perform parallel-serial conversion at two different ratios, for example, 4:1 and 5:1, two kinds of parallel-serial converters corresponding to those ratios, respectively, have to be designed, thus increasing design workload.